1. Field of the Invention
The present invention generally relates to a method for fabricating semiconductor devices, and more specifically, to a method for fabricating semiconductor devices, wherein a defect generated in a subsequent process are inhibited by minimizing the loss of a barrier metal layer of a bit line contact plug, and increases in contact resistance and bit line capacitance are a prevented to improve a process yield and reliability of the device.
2. Description of the Related Art
Recent trend in high integration of semiconductor devices is largely affected by development of a microscopic pattern formation technology. The miniaturization of a photoresist pattern, which is widely used as an etching mask or an ion-implant mask during the fabrication of a semiconductor device, is required.
A method wherein a phase shift mask (“PSM”) is used as a photo mask, a contrast enhancement layer (“CEL”) method, wherein a separate thin film is formed over a semiconductor substrate, a Tri-layer photoresist (“TLR”) method, wherein an interlayer film such as a spin on glass (“SOG”) is disposed between two photoresist films, and a Silylation method, wherein a silicon is selectively implanted onto the upper surface of a photoresist film are methods for pattern miniaturization for improving the resolution.
In addition, a contact hole connecting the lower and upper conductive wirings has a design rule larger than that of the line/space patterns. As the integration density of semiconductor devices is increased, the dimension of wirings and a space therebetween are decreased. The aspect ratio of the contact hole, which is the ratio of a diameter to a depth thereof, is increased. Therefore, a highly integrated semiconductor device including multi-layer conductive wirings requires the accurate alignment of masks during a formation process of a contact hole, thereby performing the process with a reduced process margin or without a process margin.
The masks are manufactured considering factors such as a misalignment tolerance in a mask alignment between holes, a lens distortion in a lithography process, a critical dimension variation and in a photolithography process, and a registration between masks to maintain space between contact holes.
Methods for formation of the contact hole as described above, include a direct etching method, a method using sidewall spacers and a SAC method.
The direct etching method and the method using sidewall spacers cannot be applied to fabrication of a semiconductor device having a design rule below 0.3 μm, which the limits highly integration of devices.
In addition, the SAC method designed for overcoming a limit of a lithography process during forming a contact hole can be classified according to the material used as an etch barrier layer such as a polysilicon film, a nitride film, or an oxynitride film. Among these materials, using a nitride film as the etch barrier film is widely used.
Although not shown, a method for fabricating a semiconductor device including a bit line contact having a landing plug according to a prior art will now be described.
First, a lower structure such as a device isolation oxide film, and MOSFET comprising a gate oxide film pattern, a gate electrode layer pattern and a hard mask layer pattern overlapping the gate electrode pattern are formed. An insulating film spacer consisting of a nitride film is then formed on a sidewall of the hard mask layer pattern and the gate electrode.
Next, a planarized lower interlayer insulting film is deposited over the entire surface of the resulting structure. The lower interlayer insulating film is patterned via a photolithography process using a landing plug mask to form a landing plug contact hole. Subsequently, a conductive layer for landing plug filling the contact hole is formed over the entire surface of the structure and then etched to form an electrically isolated landing plug.
Thereafter, an upper interlayer insulating layer is deposited over the entire surface of the structure. A predetermined portion of the upper interlayer insulating layer where a bit line contact is to be formed is removed to form a bit line contact.
Next, a Ti/TiN layer, which is a barrier metal film, and a W layer for a plug material are sequentially deposited over the entire surface of the structure to fill up the bit line contact hole, and then etched back to form a bit line contact plug.
In accordance with the conventional method for fabricating a semiconductor device, the barrier metal layer in the bit line contact hole is severely damaged during an etch-back process of the barrier metal film after the etch process of the W film for forming a bit line contact plug as shown in FIGS. 1 through 3. An electric short circuit may occur due to the damage to a seam at the center of the W layer. Moreover, a bit line capacitance is increased, thereby degrading the process yield and reliability of the device.
Furthermore, defect generation is accelerated in a device having design rule below 0.1 μm because the thickness of the barrier metal layer is at least greater than 30% of a contact plug.
According to the above-described prior art, a polymer on a sidewall of the W layer is ruined during an etching process due to oxygen within the interlayer insulating film since the W layer is formed on an interlayer insulating film including an oxide film. As shown in FIG. 4, the bottom of a bit line is formed with a negative slope, whereby there is another problem of increasing resistance of a bit line or causing a pattern having defects.